1. Field of the Invention
The present invention relates generally to testing integrated circuits, and more particularly to verifying minimum setup and hold times on an integrated circuit.
2. Description of Related Art
In the fabrication of integrated circuits, such as semiconductor memory devices, it is common to test the integrated circuit to verify that certain timing parameters can be met by the circuit. In the case of a synchronous dynamic random access memory (SDRAM) commands and data signals are received synchronous with a clock signal. The signals are typically supplied to the external input pins of the SDRAM within certain timing specifications. For example, signals such as the row address select (RAS), column address select (CAS), external chip select (XCS), address lines, and data lines must be supplied to the input pins a specified time period before the rising clock edge (setup time), and must be held for a specified period of time after the rising clock edge (hold time).
To test an SDRAM to verify that it meets the timing requirements, an external tester is typically connected to the external pins of the SDRAM to supply a predetermined series of level signals and pulses that simulate various commands, operating modes, and data transactions in the memory device. The external pins of the SDRAM that provide output signals are monitored to evaluate proper functioning of the SDRAM.
As the clock speeds of integrated circuits, such as SDRAMs increase, the timing requirements become more stringent. The specification for a 125 MHz or faster SDRAM requires a setup time of 2 nanoseconds (ns) and a hold time of 1 ns. These requirements may become more stringent in the future as clock speeds increase. When testing an SDRAM, it is desirable to verify the setup and hold times for the device concurrently. In the case of the 125 MHz SDRAM, such concurrent testing would require that a 3 ns pulse be supplied as an input signal on a given command, address, or data line. However, current integrated circuit testers, such as a Terradyne 994, cannot supply a 3 nanosecond pulse. Lab results were gathered on a typical 100 MHz Terradyne 994 integrated circuit tester attempting to supply a 3 ns asserted low pulse at various voltage supply levels (V.sub.IH). At V.sub.IH equal to 3V, the tester provides a 2.7 ns (midpoint to midpoint) pulse that only reaches about 0.3V at its negative peak. At V.sub.IH equal to 4V, the tester provides a 2.6 ns pulse that only reaches about 0.3V at its negative peak. At V.sub.IH equal to 5 V, the tester provides a 2.2 ns pulse that only reaches about 1.2V at its negative peak. These pulses do not have sufficient pulse width or voltage drop to effectively simulate the required timing. As a result of the inability of the tester to provide a sufficient pulse, the setup and hold times must be tested separately. This condition is undesirable because it increases testing time and expense and also does not test worst case conditions on every clock pulse. As a result, not all potential timing problems are readily observable.
It would be desirable to test timing specifications, such as setup and hold times, in integrated circuits under worst case conditions.